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| author | Anup Patel | 2022-06-16 05:15:43 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-07-03 02:03:20 +0200 |
| commit | 435774992e82d2d16f025afbb20b4f7be9b242b0 (patch) | |
| tree | e4a70542226b11f3a1a5604c3809e6aafc0100ff /target/riscv/cpu_bits.h | |
| parent | target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits (diff) | |
| download | qemu-435774992e82d2d16f025afbb20b4f7be9b242b0.tar.gz qemu-435774992e82d2d16f025afbb20b4f7be9b242b0.tar.xz qemu-435774992e82d2d16f025afbb20b4f7be9b242b0.zip | |
target/riscv: Update default priority table for local interrupts
The latest AIA draft v0.3.0 defines a relatively simpler scheme for
default priority assignments where:
1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use
and have implementation specific default priority.
2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended
(not mandatory) priority assignments.
We update the default priority table and hviprio mapping as-per above.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 157d7069f6..6be5a9e9f0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -774,7 +774,7 @@ typedef enum RISCVException { #define IPRIO_IRQ_BITS 8 #define IPRIO_MMAXIPRIO 255 #define IPRIO_DEFAULT_UPPER 4 -#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 24) +#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) |