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| author | LIU Zhiwei | 2021-12-10 08:55:55 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | 4594fa5a96d07a5087df4437aed68dbe0136ca08 (patch) | |
| tree | b5f8385c22cfa61db2501b6aff315b2409e1bf7b /target/riscv/cpu_bits.h | |
| parent | target/riscv: rvv-1.0: remove rvv related codes from fcsr registers (diff) | |
| download | qemu-4594fa5a96d07a5087df4437aed68dbe0136ca08.tar.gz qemu-4594fa5a96d07a5087df4437aed68dbe0136ca08.tar.xz qemu-4594fa5a96d07a5087df4437aed68dbe0136ca08.zip | |
target/riscv: rvv-1.0: add vcsr register
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-10-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bb62da7549..8dc6aa62c6 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -60,9 +60,16 @@ #define CSR_VSTART 0x008 #define CSR_VXSAT 0x009 #define CSR_VXRM 0x00a +#define CSR_VCSR 0x00f #define CSR_VL 0xc20 #define CSR_VTYPE 0xc21 +/* VCSR fields */ +#define VCSR_VXSAT_SHIFT 0 +#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT) +#define VCSR_VXRM_SHIFT 1 +#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT) + /* User Timers and Counters */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 |