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| author | Alistair Francis | 2020-08-12 21:13:33 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-08-25 18:11:36 +0200 |
| commit | f2d5850f71f3e41b240f328c2bc844a4e44e66c9 (patch) | |
| tree | c49500326419626349b45118db5549324af8f7db /target/riscv/cpu_bits.h | |
| parent | target/riscv: Fix the interrupt cause code (diff) | |
| download | qemu-f2d5850f71f3e41b240f328c2bc844a4e44e66c9.tar.gz qemu-f2d5850f71f3e41b240f328c2bc844a4e44e66c9.tar.xz qemu-f2d5850f71f3e41b240f328c2bc844a4e44e66c9.zip | |
target/riscv: Update the Hypervisor trap return/entry
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com
Message-Id: <e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_bits.h')
| -rw-r--r-- | target/riscv/cpu_bits.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 43617e7c1f..fb6a3e9092 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -445,6 +445,7 @@ #define HSTATUS_VTSR 0x00400000 #define HSTATUS_HU 0x00000200 #define HSTATUS_GVA 0x00000040 +#define HSTATUS_SPVP 0x00000100 #define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL |