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| author | Bin Meng | 2019-11-16 16:08:50 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-04-29 22:16:36 +0200 |
| commit | 3ca109c3f8d6225efdfa801252d25f3e526b004a (patch) | |
| tree | 320c5925140884bfa01a8f00eee99fff7aca407a /target/riscv/cpu_helper.c | |
| parent | riscv/sifive_u: Add a serial property to the sifive_u SoC (diff) | |
| download | qemu-3ca109c3f8d6225efdfa801252d25f3e526b004a.tar.gz qemu-3ca109c3f8d6225efdfa801252d25f3e526b004a.tar.xz qemu-3ca109c3f8d6225efdfa801252d25f3e526b004a.zip | |
riscv/sifive_u: Add a serial property to the sifive_u machine
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com>
[ Changed by AF:
- Use the SoC's serial property to pass the info to the SoC
- Fixup commit title
- Rebase on file restructuring
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_helper.c')
0 files changed, 0 insertions, 0 deletions