summaryrefslogtreecommitdiffstats
path: root/target/riscv/cpu_helper.c
diff options
context:
space:
mode:
authorGeorg Kotheimer2021-03-11 11:30:36 +0100
committerAlistair Francis2021-03-23 02:54:40 +0100
commitdb9ab38b81058b41e5f469165067feea46762eee (patch)
tree5c516e847992578958b66c421d001c68a114393d /target/riscv/cpu_helper.c
parenttarget/riscv: Make VSTIP and VSEIP read-only in hip (diff)
downloadqemu-db9ab38b81058b41e5f469165067feea46762eee.tar.gz
qemu-db9ab38b81058b41e5f469165067feea46762eee.tar.xz
qemu-db9ab38b81058b41e5f469165067feea46762eee.zip
target/riscv: Use background registers also for MSTATUS_MPV
The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/cpu_helper.c')
-rw-r--r--target/riscv/cpu_helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b15a60d8a2..8d4a62988d 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -364,7 +364,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
- if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+ if (!riscv_cpu_virt_enabled(env) && two_stage) {
use_background = true;
}