diff options
| author | Alistair Francis | 2020-03-27 20:53:40 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-06-19 17:24:07 +0200 |
| commit | efe9f9c820d1322729957a60ff785c9527a79ddf (patch) | |
| tree | 3fb60b5f4c86bc1f6ee5bbe9ef8d8e0ea941ee5e /target/riscv/cpu_helper.c | |
| parent | riscv: Keep the CPU init routine names consistent (diff) | |
| download | qemu-efe9f9c820d1322729957a60ff785c9527a79ddf.tar.gz qemu-efe9f9c820d1322729957a60ff785c9527a79ddf.tar.xz qemu-efe9f9c820d1322729957a60ff785c9527a79ddf.zip | |
target/riscv: Set access as data_load when validating stage-2 PTEs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv/cpu_helper.c')
| -rw-r--r-- | target/riscv/cpu_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 62fe1ecc8f..eda7057663 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -435,7 +435,7 @@ restart: hwaddr vbase; /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, &vbase_prot, base, access_type, + get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD, mmu_idx, false, true); pte_addr = vbase + idx * ptesize; |