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| author | Frank Chang | 2021-12-10 08:55:52 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | 7b07a37c2caad9252c6c5eec11ab9776826328ff (patch) | |
| tree | 9a6b4b797e1ea70b145c57f3f4f2a1d5ebddf9f0 /target/riscv/csr.c | |
| parent | target/riscv: rvv-1.0: add sstatus VS field (diff) | |
| download | qemu-7b07a37c2caad9252c6c5eec11ab9776826328ff.tar.gz qemu-7b07a37c2caad9252c6c5eec11ab9776826328ff.tar.xz qemu-7b07a37c2caad9252c6c5eec11ab9776826328ff.zip | |
target/riscv: rvv-1.0: introduce writable misa.v field
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-7-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 83f4dbd824..bc149add6c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -643,7 +643,7 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, val &= env->misa_ext_mask; /* Mask extensions that are not supported by QEMU */ - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ if ((val & RVD) && !(val & RVF)) { |