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| author | Jose Martins | 2021-05-22 17:59:02 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-07-15 00:56:00 +0200 |
| commit | bc083a51cafff73ad6113fcc81f2f40639d7c8c6 (patch) | |
| tree | a9be349b019217791b6bbf3f7a73af4b46b7f380 /target/riscv/csr.c | |
| parent | docs/system: riscv: Add documentation for virt machine (diff) | |
| download | qemu-bc083a51cafff73ad6113fcc81f2f40639d7c8c6.tar.gz qemu-bc083a51cafff73ad6113fcc81f2f40639d7c8c6.tar.xz qemu-bc083a51cafff73ad6113fcc81f2f40639d7c8c6.zip | |
target/riscv: hardwire bits in hideleg and hedeleg
The specification mandates for certain bits to be hardwired in the
hypervisor delegation registers. This was not being enforced.
Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210522155902.374439-1-josemartins90@gmail.com
[ Changes by AF:
- Improve indentation
- Convert delegable_excps to a #define to avoid failures with GCC 8
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/csr.c')
| -rw-r--r-- | target/riscv/csr.c | 54 |
1 files changed, 31 insertions, 23 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 62b968326c..9a4ed18ac5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -411,28 +411,36 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, static const target_ulong delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; +static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; -static const target_ulong delegable_excps = - (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | - (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | - (1ULL << (RISCV_EXCP_BREAKPOINT)) | - (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | - (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | - (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_U_ECALL)) | - (1ULL << (RISCV_EXCP_S_ECALL)) | - (1ULL << (RISCV_EXCP_VS_ECALL)) | - (1ULL << (RISCV_EXCP_M_ECALL)) | - (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | - (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | - (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | - (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); +#define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ + (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ + (1ULL << (RISCV_EXCP_BREAKPOINT)) | \ + (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \ + (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \ + (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_U_ECALL)) | \ + (1ULL << (RISCV_EXCP_S_ECALL)) | \ + (1ULL << (RISCV_EXCP_VS_ECALL)) | \ + (1ULL << (RISCV_EXCP_M_ECALL)) | \ + (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \ + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \ + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \ + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))) +static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS & + ~((1ULL << (RISCV_EXCP_S_ECALL)) | + (1ULL << (RISCV_EXCP_VS_ECALL)) | + (1ULL << (RISCV_EXCP_M_ECALL)) | + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; @@ -620,7 +628,7 @@ static RISCVException read_medeleg(CPURISCVState *env, int csrno, static RISCVException write_medeleg(CPURISCVState *env, int csrno, target_ulong val) { - env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps); + env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); return RISCV_EXCP_NONE; } @@ -1039,7 +1047,7 @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno, static RISCVException write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) { - env->hedeleg = val; + env->hedeleg = val & vs_delegable_excps; return RISCV_EXCP_NONE; } @@ -1053,7 +1061,7 @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno, static RISCVException write_hideleg(CPURISCVState *env, int csrno, target_ulong val) { - env->hideleg = val; + env->hideleg = val & vs_delegable_ints; return RISCV_EXCP_NONE; } |