summaryrefslogtreecommitdiffstats
path: root/target/riscv/fpu_helper.c
diff options
context:
space:
mode:
authorChih-Min Chao2021-10-21 18:08:45 +0200
committerAlistair Francis2021-10-29 08:55:45 +0200
commit0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92 (patch)
tree62971887576fbe63cded429e387ce35127ffa79b /target/riscv/fpu_helper.c
parenttarget/riscv: remove force HS exception (diff)
downloadqemu-0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92.tar.gz
qemu-0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92.tar.xz
qemu-0e9030376e1a8eb6d15cb5e69dffa09a6ff16b92.zip
softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN, The original logic: Return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan. The alternative path: Set invalid flag if ft1 == sNaN || ft2 == sNaN. Return NaN only if ft1 == NaN && ft2 == NaN. The IEEE 754 spec allows both implementation and some architecture such as riscv choose different defintions in two spec versions. (riscv-spec-v2.2 use original version, riscv-spec-20191213 changes to alternative) Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211021160847.2748577-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/fpu_helper.c')
0 files changed, 0 insertions, 0 deletions