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author | Michael Clark | 2018-03-02 13:31:11 +0100 |
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committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
commit | 9438fe7d7c54f6f897d16409d6489ddd4c99bafb (patch) | |
tree | 47cceaf6cb74e50c6f12781e6af4ed1cd4dfa268 /target/riscv/gdbstub.c | |
parent | RISC-V FPU Support (diff) | |
download | qemu-9438fe7d7c54f6f897d16409d6489ddd4c99bafb.tar.gz qemu-9438fe7d7c54f6f897d16409d6489ddd4c99bafb.tar.xz qemu-9438fe7d7c54f6f897d16409d6489ddd4c99bafb.zip |
RISC-V GDB Stub
GDB Register read and write routines.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Sagar Karandikar <sagark@eecs.berkeley.edu>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'target/riscv/gdbstub.c')
-rw-r--r-- | target/riscv/gdbstub.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c new file mode 100644 index 0000000000..4f919b6c34 --- /dev/null +++ b/target/riscv/gdbstub.c @@ -0,0 +1,62 @@ +/* + * RISC-V GDB Server Stub + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" +#include "cpu.h" + +int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (n < 32) { + return gdb_get_regl(mem_buf, env->gpr[n]); + } else if (n == 32) { + return gdb_get_regl(mem_buf, env->pc); + } else if (n < 65) { + return gdb_get_reg64(mem_buf, env->fpr[n - 33]); + } else if (n < 4096 + 65) { + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65)); + } + return 0; +} + +int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (n == 0) { + /* discard writes to x0 */ + return sizeof(target_ulong); + } else if (n < 32) { + env->gpr[n] = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n == 32) { + env->pc = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n < 65) { + env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */ + return sizeof(uint64_t); + } else if (n < 4096 + 65) { + csr_write_helper(env, ldtul_p(mem_buf), n - 65); + } + return 0; +} |