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| author | Hsiangkai Wang | 2021-12-10 08:56:54 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:53:31 +0100 |
| commit | 719d3561b269d880b2d31e64ed7632407952bad0 (patch) | |
| tree | 982331798264dc5d9883796288c53e230450d688 /target/riscv/helper.h | |
| parent | target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid (diff) | |
| download | qemu-719d3561b269d880b2d31e64ed7632407952bad0.tar.gz qemu-719d3561b269d880b2d31e64ed7632407952bad0.tar.xz qemu-719d3561b269d880b2d31e64ed7632407952bad0.zip | |
target/riscv: gdb: support vector registers for rv64 & rv32
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/helper.h')
0 files changed, 0 insertions, 0 deletions