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| author | Frédéric Pétrot | 2022-01-06 22:01:03 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-08 06:46:10 +0100 |
| commit | 7fd40f8679ceed388d82902e9be05ae136cf09cd (patch) | |
| tree | 5ed56b39753aa3b762b671ac373d96ab587a4f0a /target/riscv/helper.h | |
| parent | target/riscv: support for 128-bit shift instructions (diff) | |
| download | qemu-7fd40f8679ceed388d82902e9be05ae136cf09cd.tar.gz qemu-7fd40f8679ceed388d82902e9be05ae136cf09cd.tar.xz qemu-7fd40f8679ceed388d82902e9be05ae136cf09cd.zip | |
target/riscv: support for 128-bit arithmetic instructions
Addition of 128-bit adds and subs in their various sizes,
"set if less than"s and branches.
Refactored the code to have a comparison function used for both stls and
branches.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-14-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/helper.h')
0 files changed, 0 insertions, 0 deletions