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| author | Frank Chang | 2021-12-10 08:56:08 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | 83fcd573b121939e850d9a9836e24298d189aa79 (patch) | |
| tree | 3e0f634a51664022d2e95a25797710895016822d /target/riscv/helper.h | |
| parent | target/riscv: rvv-1.0: index load and store instructions (diff) | |
| download | qemu-83fcd573b121939e850d9a9836e24298d189aa79.tar.gz qemu-83fcd573b121939e850d9a9836e24298d189aa79.tar.xz qemu-83fcd573b121939e850d9a9836e24298d189aa79.zip | |
target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-23-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/helper.h')
0 files changed, 0 insertions, 0 deletions