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| author | Bin Meng | 2022-03-15 07:55:23 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-04-22 02:35:16 +0200 |
| commit | 95799e36c15a9ab602a388491c40f6860f6ae8bf (patch) | |
| tree | 9f91e8ed27cb9fe2b9cf437341af53daf2c33647 /target/riscv/helper.h | |
| parent | target/riscv: Allow software access to MIP SEIP (diff) | |
| download | qemu-95799e36c15a9ab602a388491c40f6860f6ae8bf.tar.gz qemu-95799e36c15a9ab602a388491c40f6860f6ae8bf.tar.xz qemu-95799e36c15a9ab602a388491c40f6860f6ae8bf.zip | |
target/riscv: Add initial support for the Sdtrig extension
This adds initial support for the Sdtrig extension via the Trigger
Module, as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220315065529.62198-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/helper.h')
0 files changed, 0 insertions, 0 deletions