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author | Frank Chang | 2021-12-10 08:56:52 +0100 |
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committer | Alistair Francis | 2021-12-20 05:53:31 +0100 |
commit | f714361ed79180a9780334cfe1b89b69f6c9bfe9 (patch) | |
tree | 424f1a7e60e908d60d3ed2083601dedfb3d1cd67 /target/riscv/helper.h | |
parent | target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits (diff) | |
download | qemu-f714361ed79180a9780334cfe1b89b69f6c9bfe9.tar.gz qemu-f714361ed79180a9780334cfe1b89b69f6c9bfe9.tar.xz qemu-f714361ed79180a9780334cfe1b89b69f6c9bfe9.zip |
target/riscv: rvv-1.0: implement vstart CSR
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first loads) to raise the memory access exception
at the exact processed vector element.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-67-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/helper.h')
-rw-r--r-- | target/riscv/helper.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 1a0d817f0f..a717a87a0e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1073,6 +1073,11 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32) + DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32) |