diff options
| author | Richard Henderson | 2019-04-01 05:11:53 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:22 +0200 |
| commit | 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2 (patch) | |
| tree | 4a26706aa4737bbc396dd43dc5ca79b67f61df06 /target/riscv/insn16-64.decode | |
| parent | target/riscv: Use pattern groups in insn16.decode (diff) | |
| download | qemu-0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2.tar.gz qemu-0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2.tar.xz qemu-0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2.zip | |
target/riscv: Split RVC32 and RVC64 insns into separate files
This eliminates all functions in insn_trans/trans_rvc.inc.c,
so the entire file can be removed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/insn16-64.decode')
| -rw-r--r-- | target/riscv/insn16-64.decode | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode new file mode 100644 index 0000000000..055859d29f --- /dev/null +++ b/target/riscv/insn16-64.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along with +# this program. If not, see <http://www.gnu.org/licenses/>. + +# *** RV64C Standard Extension (Quadrant 0) *** +ld 011 ... ... .. ... 00 @cl_d +sd 111 ... ... .. ... 00 @cs_d + +# *** RV64C Standard Extension (Quadrant 1) *** +addiw 001 . ..... ..... 01 @ci +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + +# *** RV64C Standard Extension (Quadrant 2) *** +ld 011 . ..... ..... 10 @c_ldsp +sd 111 . ..... ..... 10 @c_sdsp |