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author | Kito Cheng | 2021-05-05 18:06:11 +0200 |
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committer | Alistair Francis | 2021-06-08 01:59:45 +0200 |
commit | 91d8fc676819eff4ffcb7a8038e6de7d1dd381d3 (patch) | |
tree | b8927a78c311319b929a08bede432a2134dca1b0 /target/riscv/insn_trans/trans_rvb.c.inc | |
parent | target/riscv: rvb: single-bit instructions (diff) | |
download | qemu-91d8fc676819eff4ffcb7a8038e6de7d1dd381d3.tar.gz qemu-91d8fc676819eff4ffcb7a8038e6de7d1dd381d3.tar.xz qemu-91d8fc676819eff4ffcb7a8038e6de7d1dd381d3.zip |
target/riscv: rvb: shift ones
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210505160620.15723-11-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvb.c.inc')
-rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 69e5af44a1..28640322c4 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -155,6 +155,30 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a) return gen_shifti(ctx, a, gen_bext); } +static bool trans_slo(DisasContext *ctx, arg_slo *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_slo); +} + +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_slo); +} + +static bool trans_sro(DisasContext *ctx, arg_sro *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shift(ctx, a, gen_sro); +} + +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_shifti(ctx, a, gen_sro); +} + static bool trans_clzw(DisasContext *ctx, arg_clzw *a) { REQUIRE_64BIT(ctx); @@ -238,3 +262,31 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a) REQUIRE_EXT(ctx, RVB); return gen_shiftw(ctx, a, gen_bext); } + +static bool trans_slow(DisasContext *ctx, arg_slow *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_slo); +} + +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_slo); +} + +static bool trans_srow(DisasContext *ctx, arg_srow *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftw(ctx, a, gen_sro); +} + +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_EXT(ctx, RVB); + return gen_shiftiw(ctx, a, gen_sro); +} |