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| author | Frank Chang | 2021-12-10 08:56:12 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | a689a82b7fe65d1e09d27f7af1aead8a3ef471ce (patch) | |
| tree | 5c3f07f983d85e04adf0d9a569b2bf7f7617965f /target/riscv/insn_trans/trans_rvv.c.inc | |
| parent | target/riscv: rvv-1.0: update vext_max_elems() for load/store insns (diff) | |
| download | qemu-a689a82b7fe65d1e09d27f7af1aead8a3ef471ce.tar.gz qemu-a689a82b7fe65d1e09d27f7af1aead8a3ef471ce.tar.xz qemu-a689a82b7fe65d1e09d27f7af1aead8a3ef471ce.zip | |
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-27-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvv.c.inc')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index e12db9aae8..5c04ac90da 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1049,7 +1049,17 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale = s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} static bool opivv_check(DisasContext *s, arg_rmrr *a) { |