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| author | Frank Chang | 2021-12-10 08:56:29 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | bb45485ad1721cbbe2b35f4daad83f847bed3d36 (patch) | |
| tree | 8e6007d618fa26d10bdcb244f40146a0114839fa /target/riscv/insn_trans/trans_rvv.c.inc | |
| parent | target/riscv: rvv-1.0: single-width bit shift instructions (diff) | |
| download | qemu-bb45485ad1721cbbe2b35f4daad83f847bed3d36.tar.gz qemu-bb45485ad1721cbbe2b35f4daad83f847bed3d36.tar.xz qemu-bb45485ad1721cbbe2b35f4daad83f847bed3d36.zip | |
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-44-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvv.c.inc')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 4894212913..357615a11c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1547,7 +1547,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ /* * For vadc and vsbc, an illegal instruction exception is raised if the - * destination vector register is v0 and LMUL > 1. (Section 12.3) + * destination vector register is v0 and LMUL > 1. (Section 12.4) */ static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a) { |