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authorKito Cheng2021-12-10 08:43:21 +0100
committerAlistair Francis2021-12-20 05:51:36 +0100
commit00c1899f123713bb0629d3994fd4be26d64aeb69 (patch)
treee7454a4f77a908f79dce32de23dc44f0d306b8ee /target/riscv/internals.h
parenttarget/riscv: zfh: half-precision load and store (diff)
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target/riscv: zfh: half-precision computational
Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211210074329.5775-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
-rw-r--r--target/riscv/internals.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b15ad394bb..bce91da11a 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -58,4 +58,20 @@ static inline float32 check_nanbox_s(uint64_t f)
}
}
+static inline uint64_t nanbox_h(float16 f)
+{
+ return f | MAKE_64BIT_MASK(16, 48);
+}
+
+static inline float16 check_nanbox_h(uint64_t f)
+{
+ uint64_t mask = MAKE_64BIT_MASK(16, 48);
+
+ if (likely((f & mask) == mask)) {
+ return (uint16_t)f;
+ } else {
+ return 0x7E00u; /* default qnan */
+ }
+}
+
#endif