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authoreopXD2022-06-06 08:16:38 +0200
committerAlistair Francis2022-06-10 01:31:42 +0200
commit5c19fc156e5cea2516085c487eb72cdb331c54b6 (patch)
tree32349e82a5399525c611c1c4d2f795de4fe3ab4b /target/riscv/internals.h
parenttarget/riscv: rvv: Add tail agnostic for vector load / store instructions (diff)
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target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
`vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165449614532.19704.7000832880482980398-7@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
-rw-r--r--target/riscv/internals.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 512c6c30cf..193ce57a6d 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -25,8 +25,9 @@
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
FIELD(VDATA, VTA, 4, 1)
-FIELD(VDATA, NF, 5, 4)
-FIELD(VDATA, WD, 5, 1)
+FIELD(VDATA, VTA_ALL_1S, 5, 1)
+FIELD(VDATA, NF, 6, 4)
+FIELD(VDATA, WD, 6, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);