diff options
| author | Frank Chang | 2021-12-10 08:55:57 +0100 |
|---|---|---|
| committer | Alistair Francis | 2021-12-20 05:51:36 +0100 |
| commit | 6bc3dfa96de4173b12929824eaf80fc95d22ac28 (patch) | |
| tree | 651a05495cf41e0b382f85da89b175aa640a17ef /target/riscv/internals.h | |
| parent | target/riscv: rvv-1.0: add vlenb register (diff) | |
| download | qemu-6bc3dfa96de4173b12929824eaf80fc95d22ac28.tar.gz qemu-6bc3dfa96de4173b12929824eaf80fc95d22ac28.tar.xz qemu-6bc3dfa96de4173b12929824eaf80fc95d22ac28.zip | |
target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-12-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
0 files changed, 0 insertions, 0 deletions