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| author | LIU Zhiwei | 2020-07-01 17:25:44 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-07-02 18:19:33 +0200 |
| commit | 9fc08be626a96ae1ac0cffb22f30ae652c1c645a (patch) | |
| tree | 386fddf1edd73d8f4b55e7abf057cb76180f3d39 /target/riscv/internals.h | |
| parent | target/riscv: integer extract instruction (diff) | |
| download | qemu-9fc08be626a96ae1ac0cffb22f30ae652c1c645a.tar.gz qemu-9fc08be626a96ae1ac0cffb22f30ae652c1c645a.tar.xz qemu-9fc08be626a96ae1ac0cffb22f30ae652c1c645a.zip | |
target/riscv: integer scalar move instruction
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-57-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/internals.h')
| -rw-r--r-- | target/riscv/internals.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/internals.h b/target/riscv/internals.h index f3cea478f7..37d33820ad 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,4 +32,10 @@ FIELD(VDATA, WD, 11, 1) target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); + +#define SEW8 0 +#define SEW16 1 +#define SEW32 2 +#define SEW64 3 + #endif |