diff options
| author | Palmer Dabbelt | 2019-06-24 10:59:05 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-06-26 07:31:21 +0200 |
| commit | 50fba816cd226001bec3e495c39879deb2fa5432 (patch) | |
| tree | 0a8b056c8e90559d6a59fe53c53a8607617c08e4 /target/riscv/translate.c | |
| parent | target/riscv: Add support for disabling/enabling Counters (diff) | |
| download | qemu-50fba816cd226001bec3e495c39879deb2fa5432.tar.gz qemu-50fba816cd226001bec3e495c39879deb2fa5432.tar.xz qemu-50fba816cd226001bec3e495c39879deb2fa5432.zip | |
RISC-V: Add support for the Zifencei extension
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 313c27b700..8d6ab73258 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -54,6 +54,7 @@ typedef struct DisasContext { to any system register, which includes CSR_FRM, so we do not have to reset this known value. */ int frm; + bool ext_ifencei; } DisasContext; #ifdef TARGET_RISCV64 @@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cs->env_ptr; + RISCVCPU *cpu = RISCV_CPU(cs); ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; @@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->priv_ver = env->priv_ver; ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ + ctx->ext_ifencei = cpu->cfg.ext_ifencei; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) |