diff options
| author | Richard Henderson | 2019-04-01 05:11:51 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-05-24 21:09:22 +0200 |
| commit | 6cafec92f1c862a9754ef6a28be68ba7178a284d (patch) | |
| tree | 56b09514f750e95317e80bb2fed7188c2edf7b40 /target/riscv/translate.c | |
| parent | target/riscv: Merge argument sets for insn32 and insn16 (diff) | |
| download | qemu-6cafec92f1c862a9754ef6a28be68ba7178a284d.tar.gz qemu-6cafec92f1c862a9754ef6a28be68ba7178a284d.tar.xz qemu-6cafec92f1c862a9754ef6a28be68ba7178a284d.zip | |
target/riscv: Merge argument decode for RVC shifti
Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti. This can be handled with !function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index b09158117f..4cdffb23a4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -558,6 +558,12 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } +static int ex_rvc_shifti(DisasContext *ctx, int imm) +{ + /* For RV128 a shamt of 0 means a shift by 64. */ + return imm ? imm : 64; +} + /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" |