diff options
| author | Alistair Francis | 2020-11-04 05:43:31 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-11-10 00:08:57 +0100 |
| commit | 743077b35b1ed88ed243daefafe9403d88a958f6 (patch) | |
| tree | 762799695d3934a30887ee6725118945bb59c30c /target/riscv/translate.c | |
| parent | target/riscv: Remove the HS_TWO_STAGE flag (diff) | |
| download | qemu-743077b35b1ed88ed243daefafe9403d88a958f6.tar.gz qemu-743077b35b1ed88ed243daefafe9403d88a958f6.tar.xz qemu-743077b35b1ed88ed243daefafe9403d88a958f6.zip | |
target/riscv: Remove the hyp load and store functions
Remove the special Virtulisation load and store functions and just use
the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions
instead.
As part of this change we ensure we still run an access check to make
sure we can perform the operations.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 189ac3e53ef2854824d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..554d52a4be 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + bool hlsx; /* vector extension */ bool vill; uint8_t lmul; @@ -807,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->vlen = cpu->cfg.vlen; + ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); |