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| author | Richard Henderson | 2021-10-20 05:17:07 +0200 |
|---|---|---|
| committer | Alistair Francis | 2021-10-22 15:35:47 +0200 |
| commit | a0245d91dd1ca33ecde8c430ac6986dbd90a84db (patch) | |
| tree | e4e1bba0b06dfe341edba9892a51f5d5f0bdf283 /target/riscv/translate.c | |
| parent | target/riscv: Use gen_unary_per_ol for RVB (diff) | |
| download | qemu-a0245d91dd1ca33ecde8c430ac6986dbd90a84db.tar.gz qemu-a0245d91dd1ca33ecde8c430ac6986dbd90a84db.tar.xz qemu-a0245d91dd1ca33ecde8c430ac6986dbd90a84db.zip | |
target/riscv: Use gen_shift*_per_ol for RVB, RVI
Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f3a5870ad0..bed1c2174e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -438,6 +438,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, return true; } +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, + DisasExtend ext, + void (*f_tl)(TCGv, TCGv, target_long), + void (*f_32)(TCGv, TCGv, target_long)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift_imm_fn(ctx, a, ext, f_tl); +} + static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, void (*func)(TCGv, TCGv, TCGv)) { @@ -474,6 +490,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, return true; } +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, + void (*f_tl)(TCGv, TCGv, TCGv), + void (*f_32)(TCGv, TCGv, TCGv)) +{ + int olen = get_olen(ctx); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + f_tl = f_32; + } else { + g_assert_not_reached(); + } + } + return gen_shift(ctx, a, ext, f_tl); +} + static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, void (*func)(TCGv, TCGv)) { |