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authorBastian Koppelmann2019-02-13 16:53:48 +0100
committerBastian Koppelmann2019-03-13 10:34:06 +0100
commitd2e2c1e406e0ab886eafeb012fd2ed0d21f3a6a1 (patch)
tree9600a7598fc53bc7aa441694a0c141d39a9a1973 /target/riscv/translate.c
parenttarget/riscv: Convert RVXI csr insns to decodetree (diff)
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target/riscv: Convert RVXM insns to decodetree
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r--target/riscv/translate.c16
1 files changed, 7 insertions, 9 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18555000af..783ccade51 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1841,11 +1841,18 @@ static void decode_RV32_64C(DisasContext *ctx)
EX_SH(1)
EX_SH(12)
+#define REQUIRE_EXT(ctx, ext) do { \
+ if (!has_ext(ctx, ext)) { \
+ return false; \
+ } \
+} while (0)
+
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
+#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(DisasContext *ctx)
{
@@ -1867,15 +1874,6 @@ static void decode_RV32_64G(DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;