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| author | Richard Henderson | 2020-07-24 02:28:02 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-08-22 07:37:55 +0200 |
| commit | d36a86d01e67792c51dd2a82360cda012bde9442 (patch) | |
| tree | a57d616893325c908b885dfb6250afefbc29e53f /target/riscv/translate.c | |
| parent | target/riscv: Generate nanboxed results from fp helpers (diff) | |
| download | qemu-d36a86d01e67792c51dd2a82360cda012bde9442.tar.gz qemu-d36a86d01e67792c51dd2a82360cda012bde9442.tar.xz qemu-d36a86d01e67792c51dd2a82360cda012bde9442.zip | |
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno. Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d0485c0750..1290faddda 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -90,6 +90,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext) return ctx->misa & ext; } +/* + * RISC-V requires NaN-boxing of narrower width floating point values. + * This applies when a 32-bit value is assigned to a 64-bit FP register. + * For consistency and simplicity, we nanbox results even when the RVD + * extension is not present. + */ +static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) +{ + tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); +} + static void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); |