diff options
| author | Alistair Francis | 2019-01-15 00:58:32 +0100 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-02-12 00:56:22 +0100 |
| commit | d75377bf7bffc21f3d2b4779d8121ccab349d335 (patch) | |
| tree | 60a21b9f0833797ba2060512a4b21fe1ae755f3d /target/riscv/translate.c | |
| parent | RISC-V: Use riscv prefix consistently on cpu helpers (diff) | |
| download | qemu-d75377bf7bffc21f3d2b4779d8121ccab349d335.tar.gz qemu-d75377bf7bffc21f3d2b4779d8121ccab349d335.tar.xz qemu-d75377bf7bffc21f3d2b4779d8121ccab349d335.zip | |
RISC-V: Add priv_ver to DisasContext
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv/translate.c')
| -rw-r--r-- | target/riscv/translate.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0581b3c1f7..35eb6bdfe0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -43,6 +43,7 @@ typedef struct DisasContext { DisasContextBase base; /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; + target_ulong priv_ver; uint32_t opcode; uint32_t mstatus_fs; uint32_t mem_idx; @@ -1330,7 +1331,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, #ifndef CONFIG_USER_ONLY /* Extract funct7 value and check whether it matches SFENCE.VMA */ if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) { - if (env->priv_ver == PRIV_VERSION_1_10_0) { + if (ctx->priv_ver == PRIV_VERSION_1_10_0) { /* sfence.vma */ /* TODO: handle ASID specific fences */ gen_helper_tlb_flush(cpu_env); @@ -1384,7 +1385,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, gen_helper_wfi(cpu_env); break; case 0x104: /* SFENCE.VM */ - if (env->priv_ver <= PRIV_VERSION_1_09_1) { + if (ctx->priv_ver <= PRIV_VERSION_1_09_1) { gen_helper_tlb_flush(cpu_env); } else { gen_exception_illegal(ctx); @@ -1854,10 +1855,12 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx) static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPURISCVState *env = cs->env_ptr; ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; + ctx->priv_ver = env->priv_ver; ctx->frm = -1; /* unknown rounding mode */ } |