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| author | Tomoaki Kawada | 2022-04-17 08:02:25 +0200 |
|---|---|---|
| committer | Richard Henderson | 2022-04-21 19:09:12 +0200 |
| commit | 724eaecec6d22cf3842f896684bdc5b79492f093 (patch) | |
| tree | 052ba99c07a91da47b6dac1013f97ae95130dc23 /target/rx | |
| parent | target/rx: set PSW.I when executing wait instruction (diff) | |
| download | qemu-724eaecec6d22cf3842f896684bdc5b79492f093.tar.gz qemu-724eaecec6d22cf3842f896684bdc5b79492f093.tar.xz qemu-724eaecec6d22cf3842f896684bdc5b79492f093.zip | |
target/rx: update PC correctly in wait instruction
`cpu_pc` at this point does not necessary point to the current
instruction (i.e., the wait instruction being translated), so it's
incorrect to calculate the new value of `cpu_pc` based on this. It must
be updated with `ctx->base.pc_next`, which contains the correct address
of the next instruction.
This change fixes the wait instruction skipping the subsequent branch
when used in an idle loop like this:
0: wait
bra.b 0b
brk // should be unreachable
Signed-off-by: Tomoaki Kawada <i@yvt.jp>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220417060224.2131788-1-i@yvt.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/rx')
| -rw-r--r-- | target/rx/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/rx/translate.c b/target/rx/translate.c index 63c062993e..62aee66937 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2285,7 +2285,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) { if (is_privileged(ctx, 1)) { - tcg_gen_addi_i32(cpu_pc, cpu_pc, 2); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_wait(cpu_env); } return true; |