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| author | David Hildenbrand | 2019-08-16 10:47:06 +0200 |
|---|---|---|
| committer | Cornelia Huck | 2019-08-22 14:53:49 +0200 |
| commit | 5b773a1107e7ca6f51e3447cc066f255a7fd8cca (patch) | |
| tree | 105c7af43550cda08f4c9804fd52234764a4a4d6 /target/s390x/mmu_helper.c | |
| parent | s390x/tcg: Rework MMU selection for instruction fetches (diff) | |
| download | qemu-5b773a1107e7ca6f51e3447cc066f255a7fd8cca.tar.gz qemu-5b773a1107e7ca6f51e3447cc066f255a7fd8cca.tar.xz qemu-5b773a1107e7ca6f51e3447cc066f255a7fd8cca.zip | |
s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE
Whenever we modify a storage key, we should flush the TLBs of all CPUs,
so the MMU fault handling code can properly consider the changed storage
key (to e.g., properly set the reference and change bit on the next
accesses).
These functions are barely used in modern Linux guests, so the performance
implications are neglectable for now.
This is a preparation for better reference and change bit handling for
TCG, which will require more MMU changes.
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20190816084708.602-5-david@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x/mmu_helper.c')
0 files changed, 0 insertions, 0 deletions