diff options
| author | David Hildenbrand | 2020-09-28 14:27:14 +0200 |
|---|---|---|
| committer | Cornelia Huck | 2020-10-02 13:52:49 +0200 |
| commit | 9131bd01eceb2458abf89796d52c0eb8c5d5dace (patch) | |
| tree | 37eca859d428b0975cf1c20f1fb70aeb39204ddc /target/s390x | |
| parent | s390x/tcg: Implement MULTIPLY HALFWORD (MGH) (diff) | |
| download | qemu-9131bd01eceb2458abf89796d52c0eb8c5d5dace.tar.gz qemu-9131bd01eceb2458abf89796d52c0eb8c5d5dace.tar.xz qemu-9131bd01eceb2458abf89796d52c0eb8c5d5dace.zip | |
s390x/tcg: Implement BRANCH INDIRECT ON CONDITION (BIC)
Just like BRANCH ON CONDITION - however the address is read from memory
(always 8 bytes are read), we have to wrap the address manually. The
address is read using current CPU DAT/address-space controls, just like
ordinary data.
Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200928122717.30586-7-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x')
| -rw-r--r-- | target/s390x/insn-data.def | 2 | ||||
| -rw-r--r-- | target/s390x/translate.c | 8 |
2 files changed, 10 insertions, 0 deletions
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index bf18d8aaf4..3322e5f2a5 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -115,6 +115,8 @@ /* BRANCH RELATIVE AND SAVE */ C(0xa705, BRAS, RI_b, Z, 0, 0, r1, 0, basi, 0) C(0xc005, BRASL, RIL_b, Z, 0, 0, r1, 0, basi, 0) +/* BRANCH INDIRECT ON CONDITION */ + C(0xe347, BIC, RXY_b, MIE2,0, m2_64w, 0, 0, bc, 0) /* BRANCH ON CONDITION */ C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0) C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 66a3693d12..27fb7af8fb 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -5956,6 +5956,14 @@ static void in2_m2_64(DisasContext *s, DisasOps *o) } #define SPEC_in2_m2_64 0 +static void in2_m2_64w(DisasContext *s, DisasOps *o) +{ + in2_a2(s, o); + tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s)); + gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); +} +#define SPEC_in2_m2_64w 0 + #ifndef CONFIG_USER_ONLY static void in2_m2_64a(DisasContext *s, DisasOps *o) { |