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| author | Pavel Zbitskiy | 2018-09-02 02:33:21 +0200 |
|---|---|---|
| committer | Cornelia Huck | 2018-10-04 10:32:39 +0200 |
| commit | ae4b5a5472ede9c92b83fa908c2ec63e80b64ced (patch) | |
| tree | 2926d68bd00b1db7519bc05a39d5bcd27d7c6b13 /target/s390x | |
| parent | s390x: Fence huge pages prior to 3.1 (diff) | |
| download | qemu-ae4b5a5472ede9c92b83fa908c2ec63e80b64ced.tar.gz qemu-ae4b5a5472ede9c92b83fa908c2ec63e80b64ced.tar.xz qemu-ae4b5a5472ede9c92b83fa908c2ec63e80b64ced.zip | |
target/s390x: exception on non-aligned LPSW(E)
Both LPSW and LPSWE should raise a specification exception when their
operand is not doubleword aligned.
Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180902003322.3428-3-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Diffstat (limited to 'target/s390x')
| -rw-r--r-- | target/s390x/translate.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/s390x/translate.c b/target/s390x/translate.c index 7363aabf3a..59b1e5893c 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -2835,7 +2835,8 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o) t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), + MO_TEUL | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 4); tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s)); /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ @@ -2855,7 +2856,8 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o) t1 = tcg_temp_new_i64(); t2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s)); + tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), + MO_TEQ | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); gen_helper_load_psw(cpu_env, t1, t2); |