diff options
| author | Frédéric Pétrot | 2022-01-06 22:00:51 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-08 06:46:10 +0100 |
| commit | fc313c64345453c7a668d765610dfd7135e21a98 (patch) | |
| tree | 336a2b0e28691f2333931bf366f85e70e60f3091 /target/sh4 | |
| parent | target/riscv: Fix position of 'experimental' comment (diff) | |
| download | qemu-fc313c64345453c7a668d765610dfd7135e21a98.tar.gz qemu-fc313c64345453c7a668d765610dfd7135e21a98.tar.xz qemu-fc313c64345453c7a668d765610dfd7135e21a98.zip | |
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is
now explicit.
Done using git grep as suggested by Philippe, with a bit of hand edition to
keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/sh4')
| -rw-r--r-- | target/sh4/translate.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 50493c61ea..43bc88b7b3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1010,7 +1010,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEQ); + tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEUQ); tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); @@ -1020,7 +1020,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEUQ); gen_store_fpr64(ctx, fp, XHACK(B11_8)); tcg_temp_free_i64(fp); } else { @@ -1031,7 +1031,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEUQ); gen_store_fpr64(ctx, fp, XHACK(B11_8)); tcg_temp_free_i64(fp); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); @@ -1048,7 +1048,7 @@ static void _decode_opc(DisasContext * ctx) TCGv_i64 fp = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); tcg_gen_subi_i32(addr, REG(B11_8), 8); - tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEUQ); tcg_temp_free_i64(fp); } else { tcg_gen_subi_i32(addr, REG(B11_8), 4); @@ -1065,7 +1065,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEUQ); gen_store_fpr64(ctx, fp, XHACK(B11_8)); tcg_temp_free_i64(fp); } else { @@ -1082,7 +1082,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->tbflags & FPSCR_SZ) { TCGv_i64 fp = tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, XHACK(B7_4)); - tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEUQ); tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); |