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author | Peter Maydell | 2021-03-15 16:34:27 +0100 |
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committer | Peter Maydell | 2021-03-15 16:34:27 +0100 |
commit | 51204c2f188ec1e2a38f14718d38a3772f850a4b (patch) | |
tree | 47aae10b9baf4b79383be658168f70c446ed501d /target/tricore/translate.c | |
parent | Merge remote-tracking branch 'remotes/philmd/tags/mips-20210313' into staging (diff) | |
parent | target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 (diff) | |
download | qemu-51204c2f188ec1e2a38f14718d38a3772f850a4b.tar.gz qemu-51204c2f188ec1e2a38f14718d38a3772f850a4b.tar.xz qemu-51204c2f188ec1e2a38f14718d38a3772f850a4b.zip |
Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20210314' into staging
- Added triboard with tc27x_soc
- Cleaned up get_physical_address()
- Fixed corner case bugs in OPC2_32_RRPW_IMASK and OPC2_32_RRPW_IMASK
insns
# gpg: Signature made Sun 14 Mar 2021 13:53:11 GMT
# gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg: issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full]
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14
* remotes/bkoppelmann2/tags/pull-tricore-20210314:
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2
tricore: fixed faulty conditions for extr and imask
target/tricore: Remove unused definitions
target/tricore: Pass MMUAccessType to get_physical_address()
target/tricore: Replace magic value by MMU_DATA_LOAD definition
tricore: added triboard with tc27x_soc
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/tricore/translate.c')
-rw-r--r-- | target/tricore/translate.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 7752630ac1..2a814263de 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5777,8 +5777,8 @@ static void decode_rcpw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCPW_IMASK: CHECK_REG_PAIR(r2); - /* if pos + width > 31 undefined result */ - if (pos + width <= 31) { + /* if pos + width > 32 undefined result */ + if (pos + width <= 32) { tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); } @@ -6989,6 +6989,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) uint32_t op2; int r1, r2, r3; int32_t pos, width; + TCGv temp; op2 = MASK_OP_RRPW_OP2(ctx->opcode); r1 = MASK_OP_RRPW_S1(ctx->opcode); @@ -6999,7 +7000,12 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RRPW_EXTR: - if (pos + width <= 31) { + if (width == 0) { + tcg_gen_movi_tl(cpu_gpr_d[r3], 0); + break; + } + + if (pos + width <= 32) { /* optimize special cases */ if ((pos == 0) && (width == 8)) { tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); @@ -7021,10 +7027,15 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) break; case OPC2_32_RRPW_IMASK: CHECK_REG_PAIR(r3); - if (pos + width <= 31) { - tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); + + if (pos + width <= 32) { + temp = tcg_temp_new(); + tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + tcg_temp_free(temp); } + break; case OPC2_32_RRPW_INSERT: if (pos + width <= 32) { |