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authorLluís Vilanova2017-07-14 10:17:35 +0200
committerRichard Henderson2017-07-19 23:45:16 +0200
commit9c489ea6bed134fecfd556b439c68bba48fbe102 (patch)
tree3d54a182709bc45c16e276cc33e36f01cbe7f4ee /target/tricore
parenttcg/tci: enable bswap16_i64 (diff)
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tcg: Pass generic CPUState to gen_intermediate_code()
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target/tricore')
-rw-r--r--target/tricore/translate.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ddd2dd07dd..4e4198e887 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
}
}
-void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- TriCoreCPU *cpu = tricore_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUTriCoreState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;