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authorPeter Maydell2018-11-13 11:47:59 +0100
committerPeter Maydell2018-11-13 11:47:59 +0100
commit89430fc6f80a5aef1d4cbd6fc26b40c30793786c (patch)
tree2e739cc3a3019b51076f55977f374c4320ade883 /target/xtensa/core-dc232b.c
parenttarget/arm: Track the state of our irq lines from the GIC explicitly (diff)
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target/arm: Correctly implement handling of HCR_EL2.{VI, VF}
In commit 8a0fc3a29fc2315325400 we tried to implement HCR_EL2.{VI,VF}, but we got it wrong and had to revert it. In that commit we implemented them as simply tracking whether there is a pending virtual IRQ or virtual FIQ. This is not correct -- these bits cause a software-generated VIRQ/VFIQ, which is distinct from whether there is a hardware-generated VIRQ/VFIQ caused by the external interrupt controller. So we need to track separately the HCR_EL2 bit state and the external virq/vfiq line state, and OR the two together to get the actual pending VIRQ/VFIQ state. Fixes: 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20181109134731.11605-4-peter.maydell@linaro.org
Diffstat (limited to 'target/xtensa/core-dc232b.c')
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