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| author | Max Filippov | 2016-11-12 07:40:18 +0100 |
|---|---|---|
| committer | Max Filippov | 2017-01-15 22:01:56 +0100 |
| commit | 9e03ade4411c81a7f7d974dcedf0390835ce4096 (patch) | |
| tree | 5ed7163044ac610d041277e20def7990e507b1b5 /target/xtensa/helper.h | |
| parent | target/xtensa: fix ICACHE/DCACHE options detection (diff) | |
| download | qemu-9e03ade4411c81a7f7d974dcedf0390835ce4096.tar.gz qemu-9e03ade4411c81a7f7d974dcedf0390835ce4096.tar.xz qemu-9e03ade4411c81a7f7d974dcedf0390835ce4096.zip | |
target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/helper.h')
| -rw-r--r-- | target/xtensa/helper.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 427bdc7a3a..7e1474147b 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -23,6 +23,7 @@ DEF_HELPER_2(wsr_ccount, void, env, i32) DEF_HELPER_2(update_ccompare, void, env, i32) DEF_HELPER_1(check_interrupts, void, env) DEF_HELPER_3(check_atomctl, void, env, i32, i32) +DEF_HELPER_2(wsr_memctl, void, env, i32) DEF_HELPER_2(itlb_hit_test, void, env, i32) DEF_HELPER_2(wsr_rasid, void, env, i32) |