diff options
| author | Max Filippov | 2016-11-12 10:15:07 +0100 |
|---|---|---|
| committer | Max Filippov | 2017-01-15 22:01:56 +0100 |
| commit | 4b37aaa879d508494df14bdc49830cdf8aa77a57 (patch) | |
| tree | 65b0d726aed37ae96c2bd0c5f46e12c26132b13e /target/xtensa/overlay_tool.h | |
| parent | target/xtensa: tests: add ccount write tests (diff) | |
| download | qemu-4b37aaa879d508494df14bdc49830cdf8aa77a57.tar.gz qemu-4b37aaa879d508494df14bdc49830cdf8aa77a57.tar.xz qemu-4b37aaa879d508494df14bdc49830cdf8aa77a57.zip | |
target/xtensa: fix ICACHE/DCACHE options detection
Configuration overlay does not explicitly say whether there are ICACHE
and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect
if corresponding cache option is enabled, but that's not correct: on
cores without cache these macros are defined as 1, not as 0.
Check XCHAL_[ID]CACHE_SIZE instead.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa/overlay_tool.h')
| -rw-r--r-- | target/xtensa/overlay_tool.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 535714243b..b73fd14dd1 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -92,10 +92,10 @@ XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \ XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \ /* Local memory, TODO */ \ - XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \ + XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \ XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \ XTENSA_OPTION_ICACHE_INDEX_LOCK) | \ - XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \ + XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ |