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| author | Max Filippov | 2019-04-19 01:36:36 +0200 |
|---|---|---|
| committer | Max Filippov | 2019-05-15 19:31:52 +0200 |
| commit | 98736654f3dfbf984d9e26c9be0480b0560c1067 (patch) | |
| tree | e7f32c2f5197abc68e92c6505640865b84831b64 /target/xtensa | |
| parent | target/xtensa: implement block prefetch option opcodes (diff) | |
| download | qemu-98736654f3dfbf984d9e26c9be0480b0560c1067.tar.gz qemu-98736654f3dfbf984d9e26c9be0480b0560c1067.tar.xz qemu-98736654f3dfbf984d9e26c9be0480b0560c1067.zip | |
target/xtensa: update list of exception causes
Add XEA2 exception cause codes defined in recent Xtensa ISA releases.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa')
| -rw-r--r-- | target/xtensa/cpu.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index ba4ef2b6a7..8301923e4c 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -280,14 +280,15 @@ enum { LEVEL1_INTERRUPT_CAUSE, ALLOCA_CAUSE, INTEGER_DIVIDE_BY_ZERO_CAUSE, - PRIVILEGED_CAUSE = 8, + PC_VALUE_ERROR_CAUSE, + PRIVILEGED_CAUSE, LOAD_STORE_ALIGNMENT_CAUSE, - - INSTR_PIF_DATA_ERROR_CAUSE = 12, + EXTERNAL_REG_PRIVILEGE_CAUSE, + EXCLUSIVE_ERROR_CAUSE, + INSTR_PIF_DATA_ERROR_CAUSE, LOAD_STORE_PIF_DATA_ERROR_CAUSE, INSTR_PIF_ADDR_ERROR_CAUSE, LOAD_STORE_PIF_ADDR_ERROR_CAUSE, - INST_TLB_MISS_CAUSE, INST_TLB_MULTI_HIT_CAUSE, INST_FETCH_PRIVILEGE_CAUSE, |