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| author | Max Filippov | 2019-02-18 12:11:40 +0100 |
|---|---|---|
| committer | Max Filippov | 2019-02-28 13:43:22 +0100 |
| commit | eb3f4298c96d79a5a67b904c28f293864cc5ccc3 (patch) | |
| tree | 5cb370d2454e556508d48b6cedbdf84a13558ff2 /target/xtensa | |
| parent | target/xtensa: prioritize load/store in FLIX bundles (diff) | |
| download | qemu-eb3f4298c96d79a5a67b904c28f293864cc5ccc3.tar.gz qemu-eb3f4298c96d79a5a67b904c28f293864cc5ccc3.tar.xz qemu-eb3f4298c96d79a5a67b904c28f293864cc5ccc3.zip | |
target/xtensa: implement PREFCTL SR
Cache prefetch option adds an unprivileged SR PREFCTL. Add trivial
implementation for this SR.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'target/xtensa')
| -rw-r--r-- | target/xtensa/cpu.h | 1 | ||||
| -rw-r--r-- | target/xtensa/translate.c | 16 |
2 files changed, 17 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a01a94e2a6..4d8152682f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -131,6 +131,7 @@ enum { ACCLO = 16, ACCHI = 17, MR = 32, + PREFCTL = 40, WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 338e6ca70f..77bc04d6b0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -134,6 +134,7 @@ static const XtensaReg sregnames[256] = { [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), + [PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL), [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), [WINDOW_START] = XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), @@ -4153,6 +4154,11 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "rsr.prefctl", + .translate = translate_rsr, + .test_ill = test_ill_rsr, + .par = (const uint32_t[]){PREFCTL}, + }, { .name = "rsr.prid", .translate = translate_rsr, .test_ill = test_ill_rsr, @@ -4778,6 +4784,11 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){MMID}, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "wsr.prefctl", + .translate = translate_wsr, + .test_ill = test_ill_wsr, + .par = (const uint32_t[]){PREFCTL}, + }, { .name = "wsr.prid", .translate = translate_wsr, .test_ill = test_ill_wsr, @@ -5266,6 +5277,11 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "xsr.prefctl", + .translate = translate_xsr, + .test_ill = test_ill_xsr, + .par = (const uint32_t[]){PREFCTL}, + }, { .name = "xsr.prid", .translate = translate_xsr, .test_ill = test_ill_xsr, |