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| author | Bastian Koppelmann | 2021-03-05 14:03:51 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2021-03-14 14:48:54 +0100 |
| commit | 007479842b27e03173a333b8c2e0dae14be64f8d (patch) | |
| tree | 675d81da6392aa9d0d51f41ba85ac96c4b56f7ad /target | |
| parent | tricore: fixed faulty conditions for extr and imask (diff) | |
| download | qemu-007479842b27e03173a333b8c2e0dae14be64f8d.tar.gz qemu-007479842b27e03173a333b8c2e0dae14be64f8d.tar.xz qemu-007479842b27e03173a333b8c2e0dae14be64f8d.zip | |
target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2
if r3+1 and r2 are the same then we would overwrite r2 with our first
move and use the wrong result for the shift. Thus we store the result
from the mov in a temp.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target')
| -rw-r--r-- | target/tricore/translate.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ebeddf8f4a..5b7ed70e39 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6989,6 +6989,7 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) uint32_t op2; int r1, r2, r3; int32_t pos, width; + TCGv temp; op2 = MASK_OP_RRPW_OP2(ctx->opcode); r1 = MASK_OP_RRPW_S1(ctx->opcode); @@ -7021,10 +7022,15 @@ static void decode_rrpw_extract_insert(DisasContext *ctx) break; case OPC2_32_RRPW_IMASK: CHECK_REG_PAIR(r3); + if (pos + width <= 32) { - tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); + temp = tcg_temp_new(); + tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + tcg_temp_free(temp); } + break; case OPC2_32_RRPW_INSERT: if (pos + width <= 32) { |