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authorVineet Gupta2021-12-16 06:18:44 +0100
committerAlistair Francis2021-12-20 05:53:31 +0100
commit0643c12e4bc021ce5cb06aa1bfa02d25d8386b61 (patch)
tree7ec9051c741830554547e8a4f5dc41247b7cc05a /target
parentriscv: Set 5.4 as minimum kernel version for riscv32 (diff)
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target/riscv: Enable bitmanip Zb[abcs] instructions
The bitmanip extension has now been ratified [1] and upstream tooling (gcc/binutils) support it too, so move them out of experimental and also enable by default (for better test exposure/coverage) [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211216051844.3921088-1-vineetg@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9776297c79..6ef3314bce 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -641,10 +641,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
/* These are experimental so mark with 'x-' */
- DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
- DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
- DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
- DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
+ DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
+ DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
+ DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */