diff options
| author | Frank Chang | 2022-01-18 02:45:08 +0100 |
|---|---|---|
| committer | Alistair Francis | 2022-01-21 06:52:56 +0100 |
| commit | 13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586 (patch) | |
| tree | 760312d17640ab9bf584041180efe0fef989b7c7 /target | |
| parent | target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns (diff) | |
| download | qemu-13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586.tar.gz qemu-13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586.tar.xz qemu-13dbc826fd086dd40b7a4d3f1cb3f1bc8454b586.zip | |
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
All Zve* extensions support all vector fixed-point arithmetic
instructions, except that vsmul.vv and vsmul.vx are not supported
for EEW=64 in Zve64*.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-6-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index e64dddda28..8e493b7933 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2123,8 +2123,31 @@ GEN_OPIVX_TRANS(vasub_vx, opivx_check) GEN_OPIVX_TRANS(vasubu_vx, opivx_check) /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ -GEN_OPIVV_TRANS(vsmul_vv, opivv_check) -GEN_OPIVX_TRANS(vsmul_vx, opivx_check) + +static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + /* + * All Zve* extensions support all vector fixed-point arithmetic + * instructions, except that vsmul.vv and vsmul.vx are not supported + * for EEW=64 in Zve64*. (Section 18.2) + */ + return opivv_check(s, a) && + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); +} + +static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + /* + * All Zve* extensions support all vector fixed-point arithmetic + * instructions, except that vsmul.vv and vsmul.vx are not supported + * for EEW=64 in Zve64*. (Section 18.2) + */ + return opivx_check(s, a) && + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); +} + +GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check) +GEN_OPIVX_TRANS(vsmul_vx, vsmul_vx_check) /* Vector Single-Width Scaling Shift Instructions */ GEN_OPIVV_TRANS(vssrl_vv, opivv_check) |