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| author | Jiaxun Yang | 2022-11-02 17:57:18 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2022-11-08 01:04:25 +0100 |
| commit | 2a2105a26219695c72bfc7cab9b7d37754fc0920 (patch) | |
| tree | 818f9a0936e9ffa20f5a7ce6a8708ac1e60b97b6 /target | |
| parent | target/mips: Disable DSP ASE for Octeon68XX (diff) | |
| download | qemu-2a2105a26219695c72bfc7cab9b7d37754fc0920.tar.gz qemu-2a2105a26219695c72bfc7cab9b7d37754fc0920.tar.xz qemu-2a2105a26219695c72bfc7cab9b7d37754fc0920.zip | |
target/mips: Don't check COP1X for 64 bit FP mode
Some implementations (i.e. Loongson-2F) may decide to implement
a 64 bit FPU without implementing COP1X instructions.
As the eligibility of 64 bit FP instructions is already determined
by CP0St_FR, there is no need to check for COP1X again.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221102165719.190378-1-jiaxun.yang@flygoat.com>
[PMD: Add missing trailing parenthesis (buildfix)]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/tcg/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 4c4bd0823d..624e6b7786 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1545,7 +1545,7 @@ void check_cop1x(DisasContext *ctx) */ void check_cp1_64bitmode(DisasContext *ctx) { - if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) { + if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { gen_reserved_instruction(ctx); } } |