diff options
| author | Giuseppe Musacchio | 2020-11-13 00:01:27 +0100 |
|---|---|---|
| committer | David Gibson | 2020-12-14 05:53:26 +0100 |
| commit | 3278aa49d559ca191ff10735d363bd367d81fabf (patch) | |
| tree | 5d14b641f37e402d94cf6557f3af670a70fbb7cc /target | |
| parent | ppc: Add a missing break for PPC6xx_INPUT_TBEN (diff) | |
| download | qemu-3278aa49d559ca191ff10735d363bd367d81fabf.tar.gz qemu-3278aa49d559ca191ff10735d363bd367d81fabf.tar.xz qemu-3278aa49d559ca191ff10735d363bd367d81fabf.zip | |
ppc/translate: Fix unordered f64/f128 comparisons
According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp
- Part 1: Compare Unordered", whenever one of the two operands is a NaN
the SO bit is set while the other three bits are cleared.
Apply the same change to xscmpuqp.
The respective ordered counterparts are unaffected.
Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
Message-Id: <20201112230130.65262-2-thatlemon@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/fpu_helper.c | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 32a9a8a0f8..6d3648f5b1 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2479,13 +2479,11 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \ float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \ vxsnan_flag = true; \ - cc = CRF_SO; \ if (fpscr_ve == 0 && ordered) { \ vxvc_flag = true; \ } \ } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \ float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \ - cc = CRF_SO; \ if (ordered) { \ vxvc_flag = true; \ } \ @@ -2497,12 +2495,19 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ - if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ + switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {\ + case float_relation_less: \ cc |= CRF_LT; \ - } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ - cc |= CRF_GT; \ - } else { \ + break; \ + case float_relation_equal: \ cc |= CRF_EQ; \ + break; \ + case float_relation_greater: \ + cc |= CRF_GT; \ + break; \ + case float_relation_unordered: \ + cc |= CRF_SO; \ + break; \ } \ \ env->fpscr &= ~FP_FPCC; \ @@ -2545,12 +2550,19 @@ void helper_##op(CPUPPCState *env, uint32_t opcode, \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ - if (float128_lt(xa->f128, xb->f128, &env->fp_status)) { \ + switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) { \ + case float_relation_less: \ cc |= CRF_LT; \ - } else if (!float128_le(xa->f128, xb->f128, &env->fp_status)) { \ - cc |= CRF_GT; \ - } else { \ + break; \ + case float_relation_equal: \ cc |= CRF_EQ; \ + break; \ + case float_relation_greater: \ + cc |= CRF_GT; \ + break; \ + case float_relation_unordered: \ + cc |= CRF_SO; \ + break; \ } \ \ env->fpscr &= ~FP_FPCC; \ |