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| author | Víctor Colombo | 2022-09-06 14:55:18 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza | 2022-09-20 15:54:06 +0200 |
| commit | 34f760bac2c9a32afae150fbcc56ceba399d61de (patch) | |
| tree | ddfbbc98d6c50b6472d1b4151b9179117095e39a /target | |
| parent | target/ppc: Remove unused xer_* macros (diff) | |
| download | qemu-34f760bac2c9a32afae150fbcc56ceba399d61de.tar.gz qemu-34f760bac2c9a32afae150fbcc56ceba399d61de.tar.xz qemu-34f760bac2c9a32afae150fbcc56ceba399d61de.zip | |
target/ppc: Zero second doubleword in DFP instructions
Starting at PowerISA v3.1, the second doubleword of the registers
used to store results in DFP instructions are supposed to be zeroed.
From the ISA, chapter 7.2.1.1 Floating-Point Registers:
"""
Chapter 4. Floating-Point Facility provides 32 64-bit
FPRs. Chapter 5. Decimal Floating-Point also employs
FPRs in decimal floating-point (DFP) operations. When
VSX is implemented, the 32 FPRs are mapped to
doubleword 0 of VSRs 0-31. (...)
All instructions that operate on an FPR are redefined
to operate on doubleword element 0 of the
corresponding VSR. (...)
and the contents of doubleword element 1 of the
VSR corresponding to the target FPR or FPR pair for these
instructions are set to 0.
"""
Before, the result stored at doubleword 1 was said to be undefined.
With that, this patch changes the DFP facility to zero doubleword 1
when using set_dfp64 and set_dfp128. This fixes the behavior for ISA
3.1 while keeping the behavior correct for previous ones.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220906125523.38765-4-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/dfp_helper.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c index 5ba74b2124..be7aa5357a 100644 --- a/target/ppc/dfp_helper.c +++ b/target/ppc/dfp_helper.c @@ -42,13 +42,16 @@ static void get_dfp128(ppc_vsr_t *dst, ppc_fprp_t *dfp) static void set_dfp64(ppc_fprp_t *dfp, ppc_vsr_t *src) { - dfp->VsrD(0) = src->VsrD(1); + dfp[0].VsrD(0) = src->VsrD(1); + dfp[0].VsrD(1) = 0ULL; } static void set_dfp128(ppc_fprp_t *dfp, ppc_vsr_t *src) { dfp[0].VsrD(0) = src->VsrD(0); dfp[1].VsrD(0) = src->VsrD(1); + dfp[0].VsrD(1) = 0ULL; + dfp[1].VsrD(1) = 0ULL; } static void set_dfp128_to_avr(ppc_avr_t *dst, ppc_vsr_t *src) |