diff options
| author | Nikunj A Dadhania | 2017-03-13 10:31:04 +0100 |
|---|---|---|
| committer | David Gibson | 2017-03-14 01:27:23 +0100 |
| commit | 38a61d34875335717f22e3a0eb1e0d5df4f62def (patch) | |
| tree | 078875be99c3fa19d1c4ebe7436ae24f6e0f0e80 /target | |
| parent | target/ppc: Fix wrong number of UAMR register (diff) | |
| download | qemu-38a61d34875335717f22e3a0eb1e0d5df4f62def.tar.gz qemu-38a61d34875335717f22e3a0eb1e0d5df4f62def.tar.xz qemu-38a61d34875335717f22e3a0eb1e0d5df4f62def.zip | |
target/ppc: fix cpu_ov setting for 32-bit
A bug was introduced in following commit:
dc0ad84 target/ppc: update overflow flags for add/sub
As for 32-bit ppc target extracting bit 63 for overflow is not correct.
Made it dependent on TARGET_LOG_BITS. This had broken booting MacOS
9.2.1 image
Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b6abc60a00..f40b5a1abf 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -818,7 +818,7 @@ static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, if (is_isa300(ctx)) { tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); } - tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1); + tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); } tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); } |