diff options
| author | Richard Henderson | 2016-11-16 17:38:10 +0100 |
|---|---|---|
| committer | Richard Henderson | 2017-01-10 17:47:48 +0100 |
| commit | 3946c6aa3d402614140f2c6a044abcdfb439217a (patch) | |
| tree | b4e28b3ae3e42ebb34beedd4f7d8469a220b0a95 /target | |
| parent | target-tricore: Use clrsb helper (diff) | |
| download | qemu-3946c6aa3d402614140f2c6a044abcdfb439217a.tar.gz qemu-3946c6aa3d402614140f2c6a044abcdfb439217a.tar.xz qemu-3946c6aa3d402614140f2c6a044abcdfb439217a.zip | |
target-xtensa: Use clrsb helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
| -rw-r--r-- | target/xtensa/translate.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 5c719a4181..5a93705fac 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1372,16 +1372,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) case 14: /*NSAu*/ HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA); if (gen_window_check2(dc, RRR_S, RRR_T)) { - TCGv_i32 t0 = tcg_temp_new_i32(); - - /* if (v & 0x80000000) v = ~v; */ - tcg_gen_sari_i32(t0, cpu_R[RRR_S], 31); - tcg_gen_xor_i32(t0, t0, cpu_R[RRR_S]); - - /* r = (v ? clz(v) : 32) - 1; */ - tcg_gen_clzi_i32(t0, t0, 32); - tcg_gen_subi_i32(cpu_R[RRR_T], t0, 1); - tcg_temp_free_i32(t0); + tcg_gen_clrsb_i32(cpu_R[RRR_T], cpu_R[RRR_S]); } break; |